During typical semiconductor manufacturing processes, integrated circuits (ICs) may be tested to ensure their proper operation. Automated test equipment (ATE) may perform tests to ensure functionality and quality, with the ICs being devices-under-test (DUTs). In general, a test to be performed on a DUT consists of a set of digital pattern vectors that translate to stimulus voltage levels to be applied to input signal pins of the DUT according to a pre-specified timing. Signals captured from output signal pins of the DUT are translated into corresponding response vectors that may be analyzed to determine whether the DUT is operating according to its specification. An ATE generally provides a number of signal generating resources that may generate configurable signal levels with configurable timing(s). The tester may also provide signal processing resources capable of converting signals generated by the DUT (e.g. in analog form) into a format (e.g. in digital form) readable by the tester. The signal processing resources may also be configurable. The ATE may be configured, for example, by way of a set of relays, to electrically connect any tester resource to any tester interface pin.
A typical automated tester for integrated circuits includes a set of so-called test channels, each connected to a separate pin of an IC or DUT 130. This is schematically illustrated in FIG. 1A. FIG. 1A illustrates an ATE 100 for testing a DUT 130. The ATE 100 comprises a plurality of test channels 110-1, 110-2 to 110-n. Each of the test channels 110 is coupled to a central test control unit 120, such as, a computer or microcontroller. On the DUT-end, each of the test channels 110-1, 110-2 to 110-n is dedicated to a different input and/or output (I/O) pin of the DUT 130. Each test channel 110-1, 110-2 to 110-n may be divided into a digital and an analog signal processing part. Within the digital processing part, each test channel 110-1, 110-2 to 110-n comprises a channel-specific channel control block 111 coupled to the central test control unit 120, wherein the channel control block 111 again controls further digital test channel blocks, such as a digital test pattern generator 112 for generating digital pattern vectors, a test pattern comparator 113 for analyzing response vectors and a time formatting block 114 to generate pre-specified timings. Together, the blocks 111, 112, 113 and 114 make up a so-called digital test channel. The channel control block 111 conventionally also controls analog signal processing blocks or hardware resources 115, 116 coupled in between an I/O pin of the DUT 130 and the digital test channel. The hardware resources 115, 116 are adapted to connect the digital test channel to the DUT 130. The hardware resources 115, 116 are also adapted to convert a signal or a test pattern to/from the DUT 130 into a signal suited for the DUT-pin or the digital test channel. Hence, the hardware resources 115, 116 may comprise switches, relays, signal level drivers, threshold comparators, analog-to-digital converters (ADCs) and/or digital-to-analog converters (DACs), etc.
Conventionally, the digital test channels may be arranged in a separate digital test channel IC, while the hardware resources 115, 116 may be kept external to the digital test channel IC in order to ease their substitution, respectively. As illustrated in FIG. 1B, each of the test channels 110-1, 110-2 to 110-n may be divided into a digital test channel part 140-1, 140-2, . . . , 140-n and an analog test channel part 150-1, 150-2, . . . , 150-n, respectively. The digital test channel parts 140-1, 140-2, . . . , 140-n of the test channels 110-1, 110-2, . . . , 110-n (e.g., blocks 111, 112, 113 and 114, respectively), may be placed into a dedicated test pattern processing IC 140. The analog test channel parts 150-1, 150-2, . . . , 150-n (e.g., hardware resources 115, 116, respectively), may be located externally from the test pattern processing IC 140, in between the DUT 130 and the pattern processing IC 140.
As discussed above, the dedicated pattern processing IC 140 may be responsible for generating digital patterns that translate, via the hardware resources 150, to stimulus voltage levels to be applied to a plurality of input signal pins of the DUT 130 according to a pre-specified timing. Signals captured from a plurality of output signal pins of the DUT 130 via the hardware resources 150 may be translated into corresponding response vectors that may again be analyzed by the dedicated pattern processing IC 140. For this reason, such a chip 140 typically has a plurality of digital test channels 140-1, 140-2, . . . , 140-n. In addition, external hardware components or resources 150-1, 150-2, . . . , 150-n are needed, e.g., relays 116, or signal drivers 115, that can drive various voltages. Also, ADCs, DACs and many other hardware resources may be applied.
Traditionally, each digital test channel part 140-1, 140-2, . . . , 140-n in the pattern processing or test channel IC 140 controls its associated analog hardware resources 150-1, 150-2, . . . , 150-n, respectively. Such a setup may create great difficulties when the external resources 150-1, 150-2, . . . , 150-n are replaced for any reason with other components or resources that behave differently. Normally, the test channel IC 140 would have to be adapted in this case. However, modifying the test channel IC 140 may be an expensive and time consuming process. Also, the test software running on the central test control unit 120 may have to be adapted in case of such modifications.